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Chapter 4: Using MegaCore Functions
MegaCore Functions Design Issues
DSP Builder needs the following specific files to simulate a MegaCore function
variation:
■
■
If your MegaCore function variation is my_function , and generates in VHDL, your
design variation is in a my_function.vhd file in your design directory.
If your design is my_design , the simulation information is in a
DSPBuilder_my_design_import/my_function.vo.simdb file.
Simulating MegaCore Functions That Have a Reset Port
MegaCores functions that have a reset port must have a reset cycle at the start of
Simulink simulation to produce correct simulation results. The length of this reset
cycle must be of sufficient length, and depends on the particular MegaCore function
and parameterization.
For example, in Figure 4–11 , DSP Builder cannot tie the reset to a constant because the
simulation does not match hardware.
Figure 4–11. MegaCore Function Design With a Reset Port
You must simulate an initial reset cycle (with the step input) to replicate hardware
behavior. As in hardware, this reset cycle must be sufficiently long to propagate
through the core, which may be 50 clock cycles or more for some MegaCore functions
such as the FIR Compiler.
Additional adjustment of the reset cycles may be necessary when a MegaCore
function receives data from other MegaCore functions, to ensure that the blocks leave
the reset state in the correct order and DSP Builder delays them by the appropriate
number of cycles.
Setting the Device Family for MegaCore Functions
Most of the MegaCore functions available in DSP Builder use the IP Toolbench
interface.
DSP Builder Handbook
Volume 2: DSP Builder Standard Blockset
November 2013 Altera Corporation
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